The Wafer Question Nobody in Washington Wants to Answer Honestly
China’s semiconductor self-sufficiency target is 70% domestic wafer production. The number circulates in industry analysis and government briefings with enough regularity that it functions more as a strategic benchmark than a projection. Whether the timeline attached to it is 2030 or 2035 depends on which analyst you’re reading and what assumptions they’re making about SMIC’s yield rates and CXMT’s DRAM progress. The number itself is less important than what it implies: China has decided that semiconductor dependency is a strategic liability and is allocating national resources at a scale that makes the goal structurally achievable regardless of how long it takes.
The United States’ response — progressively tightened export controls on advanced semiconductor manufacturing equipment, restrictions on EUV lithography access via ASML, entity list additions that cut off Chinese chipmakers from US technology — was designed to extend the capability gap long enough to maintain strategic advantage. The operational result so far is more complicated than either Washington or Beijing’s public communications acknowledge. The controls have slowed China’s progress on leading-edge nodes. They have not stopped it. And in the segments of semiconductor production that don’t require cutting-edge lithography — mature nodes, memory, packaging — the controls have arguably accelerated China’s domestic buildout by eliminating the option of purchasing capability abroad.
Where China Is and Where It Isn’t
The honest assessment of China’s semiconductor position in 2026 requires separating the headline from the nuance. SMIC is producing 7nm-equivalent chips using multi-patterning techniques that work around EUV restrictions. The yield rates are lower than TSMC’s. The volume is significantly smaller. The process is more expensive per wafer. On the absolute frontier — 3nm and below, where TSMC and Samsung are shipping to Apple and NVIDIA — China has no domestic capability and no realistic path to it under current export control regimes. The gap at the frontier is real and meaningful.
In the middle and lower tiers of the market, the picture is different. Mature nodes — 28nm, 40nm, 65nm — are the chips that go into automobiles, industrial equipment, consumer appliances, and much of the infrastructure hardware that the global economy runs on. China has substantial mature-node capacity and is building more. CXMT has made progress on DRAM that closes the gap with Samsung and SK Hynix at older process nodes even as it remains well behind on HBM. YMTC’s NAND flash has been competitive in price in markets where it’s accessible. These are not the chips that power AI accelerators. They are the chips that power most of the world’s manufactured goods, and China’s position in that market is strengthening.
The 70% wafer self-sufficiency target, read against this reality, is probably achievable in the mature-node and memory segments within the stated timeframe. It is not achievable at the leading edge under current conditions. Whether that split matters more to China’s strategic goals than the frontier gap does depends on what China is actually trying to accomplish — supply chain resilience in its domestic manufacturing base, or the ability to produce frontier AI chips.
The HBM Bottleneck and Why It’s Relevant to AI
The most acute semiconductor constraint affecting AI development globally in 2026 is not lithography — it’s High Bandwidth Memory and advanced packaging. HBM is the memory architecture that allows AI accelerators to move data fast enough to take advantage of their compute capacity. NVIDIA’s H100 and H200 use SK Hynix and Samsung HBM. The AI buildout’s current ceiling is often not GPU availability but HBM availability, because the packaging processes that stack HBM dies and connect them to GPU dies are themselves constrained by equipment and process complexity.
China cannot currently produce competitive HBM for the same reason it cannot produce leading-edge logic — the equipment restrictions cut across both. CXMT’s memory progress is at older specifications. The gap on HBM specifically is larger than the gap on mature-node logic, because HBM requires both advanced DRAM technology and advanced packaging simultaneously. This is the semiconductor constraint most directly relevant to China’s ability to build domestic AI compute infrastructure, and it’s the constraint that export controls have been most effective at maintaining.
The irony is that the AI infrastructure buildout in the United States and allied countries is also straining global HBM supply. Samsung, SK Hynix, and Micron are running their HBM production lines at capacity to serve the data center market. The capital expenditure requirements to expand HBM capacity are enormous. The packaging constraint — CoWoS-class interposer technology, 2.5D integration — is a genuine bottleneck that affects every AI hardware customer globally, not just China. The export controls protected a constraint that was already under pressure from demand.
What the Self-Sufficiency Goal Means for Global Supply Chains
The trajectory of China’s semiconductor investment program — variously described as several hundred billion dollars in cumulative commitments across government funds, subsidies, and directed investment — is reorganizing global supply chains in ways that will outlast any specific export control regime. Equipment manufacturers that previously sold primarily to Chinese fabs have lost that market. Some have redirected capacity to other buyers. Others have responded by developing less restricted variants of their tools that remain accessible to Chinese customers.
The Dutch government’s restrictions on ASML’s DUV equipment exports to China — applied in 2024 under US pressure — created a scramble for existing DUV inventory inside China that inflated equipment prices globally. Chinese chipmakers accelerated purchases of any restricted equipment before restrictions took effect, creating a secondary market dynamic that temporarily benefited equipment manufacturers even as their long-term Chinese business was being restricted. The controls work with a lag that the target country can partially arbitrage.
The longer-term supply chain reorganization is more durable. Semiconductor fabs in Japan, South Korea, Taiwan, the United States, Germany, and Israel have received substantial government support in the past three years precisely because governments have concluded that geographic concentration of semiconductor production — primarily in Taiwan — is a strategic vulnerability. The US CHIPS Act, the European Chips Act, and Japan’s semiconductor investment program are responses to the same strategic calculation that China is making from the opposite direction: semiconductor dependency is a strategic liability and domestic capacity is worth paying a premium to develop.
What this produces globally is a semiconductor industry reorganizing toward redundancy. Every major economy wants domestic capacity. Every major economy is subsidizing it. The result will be more total capacity than a pure market logic would build, distributed across more geographies, with unit costs higher than a concentrated-production model. The efficiency loss is the strategic premium being paid for supply chain resilience. The question is whether the premium is worth what it buys — and whether “70% self-sufficiency” is the right benchmark for that calculation when the most strategically important chips are precisely the ones where the gap is largest.
The Technology Transfer Problem
The export control regime’s most significant structural weakness is technology transfer through talent and published research. Leading-edge semiconductor process knowledge lives in a relatively small number of engineers globally, and those engineers move. Chinese-American engineers who trained at TSMC, Intel, and Applied Materials are a resource that no export control can permanently restrict. The leading-edge process knowledge that SMIC needs to close the gap at 5nm and below exists in people, not just in equipment, and the equipment restrictions don’t prevent those people from being hired or from sharing knowledge through published research.
This is not an argument that export controls are ineffective — they clearly slow progress by removing the fastest path to capability acquisition. It’s an argument that they work on a timeline, not permanently, and that the timeline for China to develop domestic semiconductor capability at any given node is lengthened but not indefinitely extended by the current regime. The 70% self-sufficiency goal may take longer than China’s public statements imply, and it may not include the leading-edge capability that AI hardware requires. But the direction of travel is clear, the investment is committed, and the strategic logic is not going to change regardless of who is in the White House or what the trade relationship looks like in five years.
The semiconductor industry in 2026 is reorganizing around a structural reality: the technology that the next fifty years of economic and military capability will depend on is too important for any major power to remain dependent on another major power for its supply. The efficiency loss from that reorganization will show up in semiconductor prices, in product development timelines, and in the cost of AI infrastructure. It’s the price of the world that strategic competition has produced, and the 70% wafer question is how China is paying it.
The Systems Read On China’s 70% Target
The 70% semiconductor self-sufficiency target is best read as a systems-design announcement rather than a market forecast. China is declaring the shape of its compute infrastructure for the next decade, and the shape implies specific operational consequences that the trade-policy conversation tends to skip.
The first consequence is that the demand curve for non-Chinese-sourced compute inside China is being deliberately bounded. Whatever proportion of the country’s AI buildout cannot yet be served domestically is the proportion the export-control regime will compete for. As domestic capacity rises to 70%, the contested portion shrinks, and the remaining 30% becomes the high-leverage segment where U.S. and Korean suppliers can still book revenue but with progressively worse terms.
The second consequence is that the HBM bottleneck the article identifies becomes the actual constraint, and HBM does not scale linearly with general logic capacity. China can plausibly approach 70% on mature-node logic well before it can approach the same number on leading-edge memory. That gap is where the next five years of competitive policy play out, regardless of what the headline self-sufficiency percentage looks like.
Anyone reading the announcement as a single number is reading it at the wrong resolution. The system has multiple layers, each with its own catch-up curve, and the curves are not synchronised.
